The present invention relates to physical synthesis of a chip design, and more specifically, to virtual positive slack in physical synthesis.
In the chip design process, logic and physical synthesis are performed, typically iteratively at different stages of the design, to facilitate implementation of a resistor-transfer level (RTL) design in a physical form on a chip. The logic and physical synthesis (referred to generally herein as physical synthesis because the two synthesis processes provide the physical implementation) is typically done by computer automated design (CAD) tools that enforce design objectives related to performance, power usage, and area usage. The performance objective typically emphasizes timing such that the physical synthesis algorithm is primarily concerned with timing critical portions of the design. This is because the synthesis process is ultimately limited by computational resources and the time it takes to converge on a synthesis result. Thus, continuing the synthesis process indefinitely to optimize every portion of the design is impractical. However, a consequence of this emphasis on timing is that, when sufficient timing margin is achieved by a part of the design, that part is typically not worked on any longer even if power usage or area usage are sub-optimal.